The present invention relates to a method of forming a gate in a semiconductor device, and more particularly to a method of forming a tungsten polymetal gate having low resistance.
In a CMOS device, an n+ polysilicon gate could be formed in both the NMOS device and the PMOS device, by which the NMOS device would have a surface channel but the PMOS device would have a buried channel due to counter doping. The buried channel, however, contributes to the increasing short channel effect.
A dual gate forming method proposes to solve this problem by forming an n+ polysilicon gate in the NMOS device and a p+ polysilicon gate in the PMOS device. The short channel effect due to a buried channel is then no longer present as surface channels are formed in both the NMOS device and PMOS device.
However, a dual gate structure also has problems. First is the threshold voltage shift phenomenon due to leakage of boron into a channel region. Second is the gate depletion phenomenon due to out-diffusion of a p-type impurity such as boron from the p-+ polysilicon layer of the PMOS device causing insufficient impurity doping concentration in the polysilicon layer.
As to the threshold voltage shift phenomenon due to the leakage of boron into the channel region, the technique of nitridation treatment to the surface of a gate insulation layer was proposed, but there has been no suggestion for a technique directed to preventing the gate depletion phenomenon due to out-diffusion of boron.
On the other hand, the problems associated with resistance capacitance delay (RC delay) in a word line have become a serious issue that needs to be addressed as the MOSFET design rule is reduced to a sub-100 nm level. As one way to deal with the word line RC delay problems, attempts were made to apply low specific resistance materials as the gate material.
In particular, the choice of a gate material/structure is changing from a polycide gate structure having a stack of a polysilicon (Si) layer and a metal silicide layer to a polymetal gate structure having a stack of a polysilicon layer and a metal layer. For this polymetal gate structure, ways to apply tungsten (W) as the material for the metal layer of the polymetal gate (i.e., a tungsten polymetal gate) are studied.
In a tungsten polymetal gate, the polysilicon layer and the tungsten layer are brought into direct contact. This will then lead to formation of a tungsten silicide layer between the polysilicon layer and the tungsten layer in an annealing process, which causes the volume to expand and thereby induces stress. To prevent this undesirable effect, formation of a diffusion barrier between the polysilicon layer and the tungsten layer is considered essential.
Thus, a tungsten nitride (WN) layer as a diffusion barrier is formed on the polysilicon layer of the tungsten polymetal gate, and then a tungsten layer is deposited on the WN Layer.
In this case, interfacial reaction between the WN layer and the polysilicon layer at a temperature greater than 600° C. leads to the formation of an insulation layer of SiNx, introducing instability into the structure of the tungsten polymetal gate. Moreover, the resistance of the tungsten polymetal gate increases as the interfacial resistance increases due to the interfacial reaction.
More specifically, WN reacts with Si and forms W and Si3N4. W then reacts with Si forming WSi2. These interfacial reactions lead to formation of the SiNx insulation layer increasing the resistance of the tungsten polymetal gate.
To prevent the interfacial reaction, some suggestions were made to form a WSix layer or a Ti layer or a Ti/TiN layer between the tungsten nitride layer and the polysilicon layer.
Nevertheless, low resistance of the tungsten polymetal gate may be obtainable through formation of a WSix layer between the tungsten nitride layer and the polysilicon layer, but there are other problems due to the high interfacial contact resistance between polysilicon and tungsten intride in the PMOS gate causing the ring oscillator delay phenomenon.
In the case of forming a Ti layer or a Ti/TiN layer between the tungsten nitride layer and the polysilicon layer, the problems related to the high interfacial contact resistance between polysilicon and tungsten nitride in either the PMOS or the NMOS gate may not occur; however, the tungsten polymetal gate cannot achieve low resistance since the grain size of the tungsten layer deposited on the tungsten nitride layer is decreased (as shown in FIG. 1) due to crystallization of the tungsten nitride layer deposited on the Ti layer or the Ti/TiN layer.